The present invention relates to a semiconductor device, in particular, to technology which is effective when applied to a semiconductor device aiming at realization of improvement of operating speed and reduction of a leakage current of the semiconductor device, and also aiming at realization of miniaturization of the semiconductor device.
Patent Document 1 (Japanese Unexamined Patent Publication No. Hei 11 (1999)-17522) discloses the technology of providing a logic book which mixes a low-voltage threshold (Vt) device and a regular-voltage threshold (Vt) device in order to improve performance, without increasing the standby power requirement of the logic book. In the technology, the low-Vt device is used in order to raise speed, and the regular-Vt device is used in order to cut off an off-state current of the logic book. The technical idea described in Document 1 is that, in the circuit which is comprised of regular-Vt devices, a low-Vt device is used in lieu of a part of the regular-Vt devices.